Method of ONO Stack Formation

ABSTRACT

A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.

PRIORITY

This application is a continuation of U.S. patent application Ser. No.15/721,132, filed on Sep. 29, 2017, which is a continuation of U.S.patent application Ser. No. 14/942,773, filed on Nov. 16, 2015, now U.S.Pat. No. 9,793,284, issued on Oct. 17, 2017, which is a continuation ofU.S. patent application Ser. No. 14/745,217, filed on Jun. 19, 2015, nowU.S. Pat. No. 9,218,978, issued on Dec. 22, 2015, which claims priorityto U.S. Provisional Application No. 62/130,106, filed on Mar. 9, 2015,all of which are incorporated herein in their entirety.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor devices, andmore particularly to memory cells and methods of manufacturing thereofincluding an embedded or integrally formed charge-trapping gate stacksuch as an oxide-nitride-oxide (ONO) stack into an existingcomplementary metal-oxide-semiconductor (CMOS) foundry logic technology.

BACKGROUND

For many applications, such as system-on-chip, it is desirable tointegrate logic devices and interface circuits based uponmetal-oxide-semiconductor field-effect transistors (MOSFET) andnon-volatile memory (NVM) transistors on a single chip or wafer. Thisintegration can seriously impact both the MOS transistor and NVMtransistor fabrication processes. MOS transistors are typicallyfabricated using a standard or baselinecomplementary-metal-oxide-semiconductor (CMOS) process flows, involvingthe formation and patterning of conducting, semiconducting anddielectric materials. The composition of these materials, as well as thecomposition and concentration of processing reagents, and temperatureused in such a CMOS process flow are stringently controlled for eachoperation to ensure the resultant MOS transistors will functionproperly.

Non-volatile memory devices include non-volatile memory transistors,such as silicon-oxide-nitride-oxide-silicon (SONOS) based transistors,including charge-trapping gate stacks in which a stored or trappedcharge changes a threshold voltage of the NVM transistor to storeinformation as a logic 1 or 0. Charge-trapping gate stack formationinvolves the formation of a nitride or oxynitride charge-trappinglayer(s) sandwiched between two dielectric or oxide layers typicallyfabricated using materials and processes that differ significantly fromthose of the baseline CMOS process flow, and which can detrimentallyimpact or be impacted by the fabrication of the MOS transistors. Inparticular, forming a gate oxide or dielectric of a MOS transistor maysignificantly degrade performance of a previously formed charge-trappinggate stack by altering a thickness or composition of the charge-trappinglayer(s). In addition, this integration can seriously impact thebaseline CMOS process flow, and generally requires a substantial numberof mask sets and process steps, which add to the expense of fabricatingthe devices and can reduce yield of working devices.

Besides, it is imperative for the integrated fabrication process to beable to control the thickness of top oxide of NVM transistors in orderto meet requirements such as threshold voltages V_(ts) and/or equivalentoxide thickness (EOT) requirements while satisfying gate oxide thicknessrequirements of MOS transistors, especially if those MOS transistors arehigh voltage input/output (HV I/O) transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is illustrated by way of example, and not by wayof limitation, in the FIGS. of the accompanying drawings.

FIG. 1 is a flowchart illustrating an embodiment of a method forfabricating a memory cell including an embedded SONOS based NVMtransistor and MOS transistors;

FIGS. 2A-2N are representative diagrams illustrating cross-sectionalviews of a portion of a memory cell during fabrication of the memorycell according to the method of FIG. 1; and

FIG. 2O is a representative diagram illustrating a cross-sectional viewof a portion of a finished memory cell including an embedded SONOS basedNVM transistor and MOS transistors fabricated according to the method ofFIGS. 1 and 2A-2N.

DETAILED DESCRIPTION

The following description sets forth numerous specific details such asexamples of specific systems, components, methods, and so forth, inorder to provide a good understanding of several embodiments of thepresent invention. It will be apparent to one skilled in the art,however, that at least some embodiments may be practiced without thesespecific details. In other instances, well-known components or methodsare not described in detail or are presented in a simple block diagramformat in order to avoid unnecessarily obscuring the techniquesdescribed herein. Thus, the specific details set forth hereinafter aremerely exemplary. Particular implementations may vary from theseexemplary details and still be contemplated to be within the spirit andscope of the present invention.

Embodiments of a memory cell including an embedded non-volatile memory(NVM) transistor and a metal-oxide-semiconductor (MOS) transistor andmethods of fabricating the same are described herein with reference tofigures. However, particular embodiments may be practiced without one ormore of these specific details, or in combination with other knownmethods, materials, and apparatuses. In the following description,numerous specific details are set forth, such as specific materials,dimensions, concentrations and processes parameters etc. to provide athorough understanding of the present invention. In other instances,well-known semiconductor design and fabrication techniques have not beendescribed in particular detail to avoid unnecessarily obscuring thepresent invention. Reference in the description to “an embodiment”, “oneembodiment”, “an example embodiment”, “some embodiments”, and “variousembodiments” means that a particular feature, structure, orcharacteristic described in connection with the embodiment(s) isincluded in at least one embodiment of the invention. Further, theappearances of the phrases “an embodiment”, “one embodiment”, “anexample embodiment”, “some embodiments”, and “various embodiments” invarious places in the description do not necessarily all refer to thesame embodiment(s).

The description includes references to the accompanying drawings, whichform a part of the detailed description. The drawings show illustrationsin accordance with exemplary embodiments. These embodiments, which mayalso be referred to herein as “examples,” are described in enough detailto enable those skilled in the art to practice the embodiments of theclaimed subject matter described herein. The embodiments may becombined, other embodiments may be utilized, or structural, logical, andelectrical changes may be made without departing from the scope andspirit of the claimed subject matter. It should be understood that theembodiments described herein are not intended to limit the scope of thesubject matter but rather to enable one skilled in the art to practice,make, and/or use the subject matter.

The terms “over”, “under”, “between”, and “on” as used herein refer to arelative position of one layer with respect to other layers. As such,for example, one layer deposited or disposed over or under another layermay be directly in contact with the other layer or may have one or moreintervening layers. Moreover, one layer deposited or disposed betweenlayers may be directly in contact with the layers or may have one ormore intervening layers. In contrast, a first layer “on” a second layeris in contact with that second layer. Additionally, the relativeposition of one layer with respect to other layers is provided assumingoperations deposit, modify and remove films relative to a starting waferwithout consideration of the absolute orientation of the wafer.

The NVM transistor may include memory transistors or devices implementedrelated to Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) or floating gatetechnology. An embodiment of a method for integrating or embedding a NVMtransistor into a standard or baseline CMOS process flow for fabricatingone or more MOS transistors will now be described in detail withreference to FIG. 1 and FIGS. 2A through 2N. FIG. 1 is a flowchartillustrating an embodiment of a method or process flow for fabricatingthe memory cell. FIGS. 2A-2N are block diagrams illustratingcross-sectional views of a portion of a memory cell during fabricationof the memory cell according to the method of FIG. 1. FIG. 2O is arepresentative diagram illustrating a cross-sectional view of a portionof an embodiment of the finished memory cell.

Referring to FIG. 1 and FIG. 2A, the process begins with forming anumber of isolation structures 202 in a substrate or wafer 204 (step102). The isolation structures 202 isolate the memory cell being formedfrom memory cells formed in adjoining areas (not shown) of the wafer204. Optionally and additionally, isolation structures 202 may beincorporated to isolate the NVM transistor being formed in a firstregion 206 of the wafer 204 from one or more of the MOS transistorsbeing formed in a second region 208. In one embodiment, the isolationstructures 202 may include a dielectric material, such as an oxide ornitride, and may be formed by any conventional technique, including butnot limited to shallow trench isolation (STI) or local oxidation ofsilicon (LOCOS). The wafer 204 may be a bulk wafer composed of anysingle crystal material suitable for semiconductor device fabrication,or may include a top epitaxial layer of a suitable material formed on awafer. In one embodiment, suitable materials for the wafer 204 include,but are not limited to, silicon, germanium, silicon-germanium or a GroupIII-V compound semiconductor material.

Generally and optionally, as best shown in FIG. 2B, a pad oxide 209 maybe formed over a surface 216 of the wafer 204 in both the first region206 and the second region 208. In one embodiment, pad oxide 209 may besilicon dioxide (SiO₂) having a thickness of from about 10 nanometers(nm) to about 20 nm and may be grown by a thermal oxidation process orin-situ steam generation (ISSG) process.

Referring to FIG. 1 and FIG. 2B, dopants are then implanted into wafer204 through pad oxide 209 to form wells in which the NVM transistorand/or the MOS transistors will be formed, and channels for the MOStransistors (step 104). The dopants implanted may be of any type andconcentration, and may be implanted at any energy, including energiesnecessary to form wells or deep wells for the NVM transistor and/or theMOS transistors, and to form channels for the MOS transistors. In aparticular embodiment, illustrated in FIG. 2B as an example, dopants ofan appropriate ion species are implanted to form a deep N-well 210 inthe second region 208 over or in which a high-voltage (HV) MOStransistor 214, such as a MOS input/output (I/O) transistor, will beformed. In alternative embodiments, wells or deep wells can also beformed for the NVM transistor and/or a standard or low-voltage (LV) MOStransistor, such as a MOS transistor 212. It is further to beappreciated that the wells are formed by depositing and patterning amask layer, such as a photoresist layer above the surface 216 of thewafer 204, and implanting an appropriate ion species at an appropriateenergy to an appropriate concentration.

In one embodiment, channels 218 for one or more of the MOS transistors214, 212, are formed in the second region 208 of the wafer 204. As withthe well implant the channels 218 are formed by depositing andpatterning a mask layer, such as a photoresist layer above the surface216 of the wafer 204, and implanting an appropriate ion species at anappropriate energy to an appropriate concentration. For example, BF₂ canbe implanted at an energy of from about 10 to about 100 kilo-electronvolts (keV), and a dose of from about 1e12 cm⁻² to about 1e14 cm⁻² toform an N-type MOS (NMOS) transistor. A P-type MOS (PMOS) transistor maylikewise be formed by implantation of Arsenic or Phosphorous ions at anysuitable dose and energy. It is to be appreciated that implantation canbe used to form channels 218, in both of the MOS transistors 214, 212,at the same time, or at separate times using standard lithographictechniques, including a patterned photoresist layer to mask one of thechannels for the MOS transistors.

Next, referring to FIG. 1 and FIG. 2C, a patterned tunnel mask 220 isformed on or overlying the pad oxide 209, ions (represented by arrows222) of an appropriate, energy and concentration are implanted through awindow or opening in the tunnel mask to form a channel 224 for a NVMtransistor 226, and the tunnel mask and the pad oxide in at least thesecond region 208 removed (step 106). The tunnel mask can include aphotoresist layer, or a hard mask formed, from a patterned nitride orsilicon-nitride layer.

In one embodiment, the channel 224 for the NVM transistor 226 is a deepIndium doped channel implanted with Indium (In) at an energy of fromabout 50 to about 500 kilo-electron volts (keV), and a dose of fromabout Sell cm⁻² to about 1e13 cm⁻² to form an n-channel NVM transistor.In one embodiment, implanting Indium to form the channel 224 of the NVMtransistor 226 improves the threshold voltage (V_(T)) uniformity of theNVM transistor from a sigma of V_(T) from about 150 millivolts (mV) tofrom about 70 to 80 mV. Optionally or additionally, a shallow dopedchannel is implanted with Arsenic at an energy about 20 keV and a doseof from about 5e11 cm⁻² to about 1e13 cm⁻² at channel 224.Alternatively, BF₂ may be implanted to form an n-channel NVM transistor,or Arsenic or Phosphorous implanted to form a p-channel NVM transistor.In one alternative embodiment, channel for NVM transistor 226 may alsobe formed concurrently with channels 218 of the MOS transistors 214,212.

A photoresist tunnel mask 220 can be ashed or stripped using oxygenplasma. A hard mask can be removed using a wet or dry etch process. Thepad oxide 209 is removed, for example in a wet clean process using a10:1 buffered oxide etch (BOE) containing a surfactant. Alternatively,the wet clean process can be performed using a 20:1 BOE wet etch, a 50:1hydrofluoric (HF) wet etch, a pad etch, or any other similarhydrofluoric-based wet etching chemistry.

Referring to FIG. 1 and FIGS. 2D-2F, the surface 209 of the wafer 204 iscleaned or precleaned, a number of dielectric layers, such asoxide-nitride-oxide or ONO layers or oxide-nitride-oxide-nitride-oxideor ONONO layers, formed or deposited, a mask formed on or overlying thedielectric layers, and the dielectric layers etched to form a dielectricgate stack 236 in the first region 206 (step 108). The preclean can be awet or dry process and in this embodiment is wet process using HF orstandard cleans (SC1) and (SC2), and is highly selective to the materialof the wafer 204. In one embodiment, SC1 is typically performed using a1:1:5 solution of ammonium hydroxide (NH₄OH), hydrogen peroxide (H₂O₂)and water (H₂O) at 30° C. to 80° C. for about 10 minutes. In anotherembodiment, SC2 is a short immersion in a 1:1:10 solution of HCl, H₂O₂and H₂O at about 30° C. to 80° C.

Referring to FIG. 2D, the dielectric or ONO or ONONO deposition beginswith the formation of a tunnel dielectric 228 over at least the channel224 of the NVM transistor 226 in the first region 206 of the wafer 204,and may spread over to the second region 208 of wafer 204 where MOStransistor(s) is. The tunnel dielectric 228 may be any material and haveany thickness suitable to allow charge carriers to tunnel into anoverlying charge-trapping layer under an applied gate bias whilemaintaining a suitable barrier to leakage when the NVM transistor isunbiased. In certain embodiments, tunnel dielectric 228 is silicondioxide, silicon oxy-nitride, or a combination thereof and can be grownby a thermal oxidation process, using ISSG or radical oxidation.

In one embodiment a silicon dioxide tunnel dielectric 228 may bethermally grown in a thermal oxidation process. For example, a layer ofsilicon dioxide may be grown utilizing dry oxidation at 750° C.-800° C.in an oxygen containing gas or atmosphere, such as oxygen (O₂) gas. Thethermal oxidation process is carried out for a duration approximately inthe range of 50 to 150 minutes to effect growth of a tunnel dielectric228 having a thickness of from about 1.0 nanometers (nm) to about 3.0 nmby oxidation and consumption of the exposed surface of wafer.

In another embodiment, a silicon dioxide tunnel dielectric 228 may begrown in a radical oxidation process involving flowing hydrogen (H₂) andoxygen (O₂) gas into a processing chamber at a ratio to one another ofapproximately 1:1 without an ignition event, such as forming of aplasma, which would otherwise typically be used to pyrolyze the H₂ andO₂ to form steam. Instead, the H₂ and O₂ are permitted to react at atemperature approximately in the range of about 900° C. to about 1100°C. at a pressure approximately in the range of about 0.5 Torr to about10 Torr to form radicals, such as, an OH radical, an HO₂ radical or an Odiradical, at the surface of wafer. The radical oxidation process iscarried out for a duration approximately in the approximate range ofabout 1 to about 10 minutes to effect growth of a tunnel dielectric 228having a thickness of from about 1.0 nanometers (nm) to about 4.0 nm byoxidation and consumption of the exposed surface of wafer. It will beunderstood that in FIG. 2D and in subsequent figures the thickness oftunnel dielectric 228 is exaggerated relative to the pad oxide 209,which is approximately 7 times thicker, for the purposes of clarity. Inone embodiment, a tunnel dielectric 228 grown in a radical oxidationprocess may be both denser and composed of substantially fewer hydrogenatoms/cm³ than a tunnel dielectric formed by wet oxidation techniques,even at a reduced thickness. In certain embodiments, the radicaloxidation process is carried out in a batch-processing chamber orfurnace capable of processing multiple wafers to provide a high qualitytunnel dielectric 228 without impacting the throughput (wafers/hr.)requirements that a fabrication facility may require.

In another embodiment, tunnel dielectric layer 228 is deposited bychemical vapor deposition (CVD) or atomic layer deposition and iscomposed of a dielectric layer which may include, but is not limited tosilicon dioxide, silicon oxy-nitride, silicon nitride, aluminum oxide,hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate,hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide. In yetanother embodiment, tunnel dielectric 228 may be a bi-layer dielectricregion including a bottom layer of a material such as, but not limitedto, silicon dioxide or silicon oxy-nitride and a top layer of a materialwhich may include, but is not limited to silicon nitride, aluminumoxide, hafnium oxide, zirconium oxide, hafnium silicate, zirconiumsilicate, hafnium oxy-nitride, hafnium zirconium oxide and lanthanumoxide.

Referring again to FIG. 2D, a charge-trapping layer is formed on oroverlying the tunnel dielectric 228. Generally, as in the embodimentshown, the charge-trapping layer is a multi-layer charge-trapping layer230 comprising multiple layers including at least a lower or firstcharge-trapping layer 230 a which is closer to the tunnel dielectric228, and an upper or second charge-trapping layer 230 b that isoxygen-lean relative to the first charge-trapping layer and comprises amajority of a charge traps distributed in multi-layer charge-trappinglayer.

The first charge-trapping layer 230 a of a multi-layer charge-trappinglayer 230 may include a silicon nitride (Si₃N₄), silicon-rich siliconnitride or a silicon oxy-nitride (SiO_(x)N_(y)(HO)) layer. For example,the first charge-trapping layer 230 a may include a silicon oxynitridelayer having a thickness of between about 2.0 nm and about 6.0 nm formedby a CVD process using dichlorosilane (DCS)/ammonia (NH₃) and nitrousoxide (N₂O)/NH₃ gas mixtures in ratios and at flow rates tailored toprovide a silicon-rich and oxygen-rich oxynitride layer.

The second charge-trapping layer 230 b of the multi-layercharge-trapping layer 230 is then formed, either directly or indirectly,over the first charge-trapping layer 230 a. In one embodiment, thesecond charge-trapping layer 230 b may include a silicon nitride andsilicon oxy-nitride layer having a stoichiometric composition of oxygen,nitrogen and/or silicon that is different from that of the firstcharge-trapping layer 230 a. The second charge-trapping layer 230 b mayinclude a silicon oxynitride layer having a thickness of between about2.0 nm and about 8.0 nm, and may be formed or deposited by a CVD processusing a process gas including DCS/NH₃ and N₂O/NH₃ gas mixtures in ratiosand at flow rates tailored to provide a silicon-rich, oxygen-lean topnitride layer. In one alternative embodiment, the stoichiometriccomposition of oxygen, nitrogen and/or silicon of first and secondcharge-trapping layers 230 a&b may be identical or approximate to oneanother.

In another embodiment, there may be a dielectric and/or oxide layer (notshown) formed between the first and second charge-trapping layers 230 aand 230 b, making the multi-layer charge trapping layer 230 an NONstack. In some embodiments, the multi-layer charge-trapping layer 230 isa split charge-trapping layer, further including a thin, middle oxidelayer (not shown) separating the first (lower) and second (upper)charge-trapping layers 230 a and 230 b. The middle oxide layersubstantially reduces the probability of electron charge thataccumulates at the boundaries of the second charge-trapping layer 230 bduring programming from tunneling into the first charge-trapping layer230 a, resulting in lower leakage current than for the conventionalmemory devices. In one embodiment, the middle oxide layer is formed byoxidizing to a chosen depth using thermal or radical oxidation. Radicaloxidation may be performed, for example, at a temperature of 1000-1100°C. using a single wafer tool, or 800-900° C. using a batch reactor tool.A mixture of H₂ and O₂ gasses may be introduced to a process chamber ata ratio of approximately 1:1 and 10-15 Torr using a single wafer tool,or a pressure of 300-500 Torr for a batch process, for a time of 1-2minutes using a single wafer tool, or 30 min to 1 hour using a batchprocess. In some embodiments, the radical oxidation process is withoutan ignition event, such as forming of plasma, which would otherwisetypically be used to pyrolyze the H₂ and O₂ to form steam. Instead, theH₂ and O₂ is permitted to react at a surface of the firstcharge-trapping layer 230 a to form radicals, such as, an OH radical, anHO₂ radical or an O diradical, to form the middle oxide layer.

As used herein, the terms “oxygen-rich” and “silicon-rich” are relativeto a stoichiometric silicon nitride, or “nitride,” commonly employed inthe art having a composition of (Si₃N₄) and with a refractive index (RI)of approximately 2.0. Thus, “oxygen-rich” silicon oxynitride entails ashift from stoichiometric silicon nitride toward a higher weight % ofsilicon and oxygen (i.e. reduction of nitrogen). An oxygen rich siliconoxynitride film is therefore more like silicon dioxide and the RI isreduced toward the 1.45 RI of pure silicon dioxide. Similarly, filmsdescribed herein as “silicon-rich” entail a shift from stoichiometricsilicon nitride toward a higher weight % of silicon with less oxygenthan an “oxygen-rich” film. A silicon-rich silicon oxynitride film istherefore more like silicon and the RI is increased toward the 3.5 RI ofpure silicon.

Referring again to FIG. 2D, the number of dielectric layers furtherincludes a cap layer 232 that is formed on or overlying thecharge-trapping layer 230. In one embodiment, the cap layer 232 includesa silicon nitride all or part of which is subsequently oxidized to forma blocking oxide overlying the charge-trapping layer 230. In a fewembodiments, cap layer 232 may be a single layer of nitride (not shown)having a homogeneous composition, a single layer of nitride having agradient in stoichiometric composition, or, as in the embodiment shown,may be a multi-layer cap layer including at least a lower or first caplayer 232 a overlying the second charge-trapping layer 230 b, and anupper or second cap layer 232 b overlying the first cap layer 232 a.

In one embodiment, the first cap layer 232 a can include a siliconnitride, a silicon-rich silicon nitride or a silicon-rich siliconoxynitride layer having a thickness of between 2.0 nm and 4.0 nm formedby a CVD process using N₂O/NH₃ and DCS/NH₃ gas mixtures. Similarly, thesecond cap layer 232 b can also include a silicon nitride, asilicon-rich silicon nitride or a silicon-rich silicon oxynitride layerhaving a thickness of between 2.0 nm and 4.0 nm formed by a CVD processusing N₂O/NH₃ and DCS/NH₃ gas mixtures. Optionally, the first cap layer232 a and second cap layer 232 b may comprise different stoichiometricratio. For example, the second cap layer 232 b may comprise a silicon oroxygen rich composition relative to the first cap layer 232 a tofacilitate removal of the second cap layer in a dry or wet clean processprior to oxidizing the first cap layer 232 a. Alternatively, the firstcap layer 232 a may comprise a silicon or oxygen rich compositionrelative to the second cap layer 232 b to facilitate oxidation of thefirst cap layer 232 a.

Referring to FIG. 2E, a sacrificial oxide layer 234 is formed on oroverlying the second cap layer 232 b. In one embodiment, the sacrificialoxide layer 234 may be formed or deposited by a chemical vapordeposition process in a low pressure chemical vapor deposition (LPCVD)chamber. For example, the sacrificial oxide layer 234 may be depositedby a CVD process using a process gas including gas mixtures of silane ordichlorosilane (DCS) and an oxygen containing gas, such as O₂ or N₂O, inratios and at flow rates tailored to provide a silicon dioxide (SiO₂)sacrificial oxide layer. In another embodiment, the sacrificial oxidelayer 234 may include a silicon dioxide layer grown by a thermaloxidation process, in-situ steam generation (ISSG), or radicaloxidation, and having a thickness of approximately between 2.0 nm and4.0 nm.

Referring to FIG. 2F, a patterned mask layer (not shown) is formed on oroverlying the sacrificial oxide layer 234. Subsequently, the sacrificialoxide layer 234, cap layers 232 a&b, and the charge-trapping layers 230a&b are etched or patterned to form a gate stack 236 overlying thechannel 224 of the NVM transistor 226 and sacrificial oxide layer 234,cap layers 232 a&b, and charge trapping layers 230 a&b from the secondregion 208 of the wafer 204 are removed. In one embodiment, thepatterned mask layer (not shown) may include a photoresist layerpatterned using standard lithographic techniques, and sacrificial oxidelayer 234, cap layer 232, and charge trapping layer 230 may be etched orremoved using a dry etch process including one or more separate steps tostop at tunnel dielectric layer 228 or proximate to surface 216 of wafer204.

Referring to FIG. 1, a gate oxide or GOX preclean is performed, gateoxides for both MOS transistors 214, 212 formed, and a gate layer isdeposited and patterned to form gates for the NVM transistor 226, andboth MOS transistors (step 110). Referring to FIG. 2G, during the GOXpreclean process, sacrificial oxide layer 234 of gate stack 236 and aportion of the cap layer 232 or substantially of all of a top mostlayer, such as second cap layer 232 b, in a multi-layer cap layer 232are removed from the gate stack 236 in a highly selective cleaningprocess. In certain embodiments, the highly selective cleaning processmay even remove a portion of first cap layer 232 a. In one embodiment,this cleaning process may simultaneously or concurrently further removeany residual oxide, such as an oxide tunnel dielectric 228 and pad oxide209, remaining in the first region 206 outside of the gate stack 236 andin the second region 208 to prepare the wafer 204 in that region forgate oxide growth. In one embodiment, the thickness of cap layer 232 isadjusted to allow a portion or substantially all of second cap layer 232b, may even be a portion of first cap layer 232 a, to be consumed by theGOX preclean. In one embodiment, sacrificial oxide layer 234 and secondcap layer 232 b are removed in a wet clean process using a 10:1 bufferedoxide etch (BOE) containing a surfactant. Alternatively, the wet cleanprocess can be performed using a 20:1 BOE wet etch, a 50:1 hydrofluoric(HF) wet etch, a pad etch, or any other similar hydrofluoric-based wetetching chemistry.

This embodiment of the GOX preclean is advantageous in that itsubstantially does not affect the baseline CMOS process, either in thepreclean step (step 110) or a subsequent oxidation step (step 112), butrather uses it for the integration of the NVM transistor fabrication.

Referring to FIGS. 2H and 21, in one embodiment, a two-step oxidationprocess is performed consecutively to oxidize at least the remainingportion of the cap layer 232 or the first cap layer 232 a of amulti-layer cap layer, or a portion of the second charge-trapping layer230 b to form a blocking oxide layer 238 overlying the secondcharge-trapping layer 230 b. In one embodiment, the two-step oxidationprocess is adapted to oxidize the first cap layer 232 a to form theblocking oxide layer 238 while simultaneously or concurrently oxidizingat least a portion of the surface 216 of the wafer 204 in the secondregion 208 to form gate oxide 240 overlying at least the channel 218 ofat least one MOS transistor. Accordingly, in general it is imperative tobe able to configure the two-step oxidation process in order to growboth top oxide layer of the NVM transistor 226 and gate oxide(s) of theMOS transistor(s) 212, 214 to their respective desirable operationalthicknesses. In one embodiment, gate oxide thicknesses are such that thefinal top oxide of NVM transistor 226 was approximately 30-45 Å thick inorder to meet the requirements for the reliability of the ONO stack.However, in some other embodiments, the MOS transistor(s) may be an I/Otransistor in which their I/O gate oxide is required to be much thickerin order to support a higher I/O voltage. For instance, in oneembodiment, one of the MOS transistors in the region 208 is a highvoltage I/O transistor and thus requires a thick gate oxide (over 100 Åto 200 Å). In such process flows, while the I/O gate oxide may achieveits required thickness, since they are subjected to the same environmentduring oxidation of the gate oxide of MOS transistor(s), top oxide ofthe NVM transistor 226 may be grown too thick. As a result, the NVMtransistor 226 may not meet the requirements for effective oxidethickness (EOT) and program/erase V_(ts). Alternatively, the depositedtop oxide may be protected and be the top oxide in the final NVM stack,the reliability of the NVM stack may however be negatively impacted bythe inferior quality top oxide.

Therefore, in one embodiment, a novel two-step oxidation process isproposed to ensure desirable top oxide 238 of NVM transistor 226 andgate oxide 240 of MOS transistor(s) thicknesses are both achieved whilemaintain the quality of the grown oxide layers. In one embodiment, thefirst step is a rapid thermal dry oxidation (RTO) and the second step isa rapid and radical wet oxidation such as in-situ steam generation(ISSG). Referring to FIG. 2H, the oxidation process starts with dry RTOperformed in a batch or single wafer processing chamber with or withoutan ignition event such as plasma. For example, in one embodiment, thedevice is subjected to a rapid thermal oxidation process involvingflowing oxygen (O₂) gas into a processing chamber. The O₂ gas ispermitted to react at a temperature approximately in the range of1000-1100° C. at a pressure approximately in the range of 0.5-5 Torr toform a bottom layer of first gate oxide 240 a. In one embodiment, abottom layer of first gate oxide 240 a is grown, by oxidizing siliconwafer 204, on at least a portion of the surface 216 of the wafer 204 inthe second region 208 overlying at least the channel 218 of at least oneMOS transistor, and in the first region 206 outside of gate stack 236.However, in one embodiment, the dry RTO process has very little to noeffect on first cap layer 232 a of ONO gate stack 236, which is anitride or oxynitride, and virtually no oxide is grown on gate stack236. In one alternative embodiment, dry RTO process may be substitutedwith a rapid molecular oxidation (dry or wet) which is a non-radicaloxidation process. Since there is no radical formed during the process,the first cap layer 232 a, which is a nitride or oxynitride, will havevirtually no oxide grown on gate stack 236 while a bottom layer of firstgate oxide 240 a is formed, on at least a portion of the surface 216 ofthe wafer 204 in the second region 208 overlying at least the channel218 of at least one MOS transistor. In one embodiment, after the dry RTOoxidation process, or one of its alternative oxidation processes, abottom layer of first gate oxide 240 a may have a thickness of fromabout 85 Å to about 95 Å and more.

After a desirable thickness of first gate oxide bottom layer 240 a isgrown, the oxidation process may progress immediately to a separatedstep of a second wet rapid and radical oxidation process such as in-situsteam generation (ISSG). Referring to FIG. 2I, for example, wet rapidand radical oxidation may be performed in a batch or single waferprocessing chamber with or without an ignition event such as plasma. Forexample, in one embodiment the blocking oxide layer 238 and a top layerof first gate oxide 240 b may be grown in a wet radical oxidationprocess involving flowing hydrogen (H₂) and oxygen (O₂) gas into aprocessing chamber at a ratio to one another of approximately 1:1without an ignition event, such as forming of a plasma, which wouldotherwise typically be used to pyrolyze the H₂ and O₂ to form steam.Instead, the H₂ and O₂ are permitted to react at a temperatureapproximately in the range of 1000-1100° C. at a pressure approximatelyin the range of 0.5-10 Torr to form radicals, such as, an OH radical, anHO₂ radical or an O diradical radicals at a surface of the cap layer 232or the first cap layer 232 a. The oxidation process is carried out for aduration approximately in the range of 1-5 minutes for a single waferusing an ISSG process, or 30-120 minutes for a batch furnace process toeffect growth of a blocking oxide layer 238 by oxidation and consumptionof the first cap layer 232 a and may be a portion of the secondcharge-trapping layer 230 b. During the same period, a top layer offirst gate oxide 240 b is grown on the first gate oxide bottom layer 240a in the second region 208 overlying at least the channel 218 of atleast one MOS transistor. In one embodiment, after the second wetradical oxidation process such as ISSG, blocking oxide layer 238 mayhave a thickness of from about 30 Å to about 45 Å. Simultaneously, firstgate oxide top layer 240 b is grown to complete formation of gate oxidelayer 240 to a thickness of from about 105 Å to about 200 Å. Inalternative embodiments, the second step wet rapid and radical oxidationmay be substituted by processes such as chemical vapor deposition (CVD),or other radical oxidation processes performed in a batch or singlewafer processing chamber with or without an ignition event such asplasma as long as oxide will be grown or deposited both on gate stack236 of NVM transistor and first gate oxide bottom layer 240 a of MOStransistor(s) simultaneously. In one embodiment, after the two stepoxidation process as previously described, the thickness ratio betweentop oxide 238 of NVM transistor and gate oxide 240 of at least one ofthe MOS transistor is in an approximate range of 1:2.33 (105 nm/45 nm)to 1:6.67 (200/30 nm).

In one embodiment, by controlling the parameters in the first step dryRTO process and the second step wet ISSG process such as time duration,temperature, pressure, reactants etc., targeted thicknesses of blockingoxide layer 238 of NVM transistor in the first region 206 and gate oxidelayer 240 of at least one MOS transistor in the second region 208 areachieved. The following table illustrates an example of implementationof the proposed two-step oxidation process:

Top Oxide Grown Oxide (SONOS) Gate Oxide (MOS) Oxidation Process(Silicon) Thickness Thickness Thickness Dry RTO 100 Å  0 Å  95 Å WetISSG  70 Å 45 Å 115 Å

In this example, the dry RTO process (first oxidation step) that growsabout 100 Å of oxide on silicon, may grow about 95 Å of oxide in thesecond region 208 on the wafer 204 and has very little effect on thefirst cap layer 232 a which is a nitride or oxynitride. The wet ISSGprocess (second oxidation step), which normally grows 70 Å of oxide onsilicon, builds the thickness of gate oxide 240 in the second region 208on the wafer 204 up to approximately 115 Å which may be the target for aHV I/O gate oxide in one embodiment. The top oxide of the ONNO or ONONOgate stack 236 grows only during the wet ISSG process. For 70 Åoxidation on silicon, approximately 45 Å oxide is grown on by consumingthe nitride in first cap layer 232 a and maybe second charge trappinglayer 230 b of gate stack 236. In one embodiment, a target thickness ofabout 45 Å for a top oxide of a SONOS may be desirable to meet EOT andV_(ts) requirements. In other embodiments, parameters of the rapid drythermal oxidation and radical wet oxidation may be adjusted to attaindesirable top oxide thicknesses for the NVM transistor and MOStransistor in one single process. Besides, using rapid thermal processesfor both oxidations minimizes the interaction between the STI gapfilldielectric, such as dielectric in isolation structures 202 and the ONOstack. It minimizes the moisture in the gap fill dielectric from gettingout and affecting the ONO thicknesses which may impact the V_(ts) of theSONOS device.

In one embodiment, the two gate oxidation steps are carried out insingle wafer tools. The dry thermal oxidation and wet radical oxidationprocesses can be either done in two different tools such as a rapidthermal anneal (RTA) single wafer tool for the dry RTO process andsubsequently an ISSG single wafer tool for the ISSG process.Alternatively, dry and wet RTO may be carried out in one ISSG tool. Inthis particular embodiment, the oxidation is initially performed byraising the wafer temperature to 1000-1100° C. range and flowing O₂ onlyfor a required amount of time to finish the dry RTO process.Subsequently, H₂ is introduced in order to start the ISSG oxidation. Theoperation temperature of the two oxidation steps is preferably kept atthe same value.

In one alternative embodiment, the sequence of the dry RTO and wet ISSGoxidation steps may be reversed. The device is first subjected to wetISSG oxidation either in a batch or single wafer processing chamber withor without an ignition event such as plasma, wherein top oxide 238′ maybe grown on both gate stack 236 of NVM transistor and first gate oxidebottom layer 240 a′ in the second region 208 overlying at least thechannel 218 of at least one MOS transistor. The wet ISSG oxidation maybe terminated when a desirable thickness of top oxide 238′ of NVMtransistor 236 is attained. Subsequently, a dry RTO step may begin tocontinue growing first gate oxide top layer 240 b′ on first gate oxidebottom layer 240 a′ until a desirable combined thickness of gate oxide240 is attained. The dry RTO step has very little to no effect on thethickness of top oxide 238′ of NVM transistor 236 that was grown duringthe wet ISSG oxidation.

In another alternative embodiment, both oxidation steps are done in ISSGprocess, hence both oxidation steps will oxidize first cap layer 232 aof gate stack 236 of NVM transistor. In this embodiment, after the firstISSG oxidation step, a photomask is applied such that only gate stack236 of NVM transistor regions is exposed by using photoresist. Usingthis photomask, a HF etch is carried out to remove only the oxide grownon and consuming a portion of the nitride in first cap layer 232 a inNVM transistor. Following the edge process, the photoresist is removedand the wafer is subjected to a second wet ISSG process to form the restof gate oxide 240 of MOS transistor and also form top oxide 238 of NVMtransistor by consuming the rest of first cap layer 232 a until adesirable thickness is attained. In this particular embodiment, an extraphotomask may be required.

In some embodiments, as explained briefly above, the dry radical RTOstep and/or wet radical ISSG oxidation step may be carried out at abatch furnace. In these embodiments, the process flow is the same but ineach oxidation, a batch of wafers (100-125 wafers) are subjected to theoxidation concurrently. This embodiment assumes that a capable batchtype tool for radical oxidation is available. For this scheme to besuccessful, the gap fill dielectric, such as dielectric in isolationstructures 202 and the ONO stack, needs to be of high quality with zeroor minimum moisture content.

In one embodiment, the grown gate oxide 240, which includes a layer offirst gate oxide bottom layer 240 a grown during the first oxidationstep and first gate oxide top layer 240 b during the second oxidationstep, may or may not exhibit different stoichiometric ratio and/orstructures between gate oxide layers 240 a and 240 b.

In some embodiments, such as that shown in FIGS. 2J to 2N, the methodfurther includes a dual gate oxide process flow to enable fabrication ofboth a LV MOS transistor 212 and a HV MOS transistor 214. Referring toFIG. 2J, a patterned mask layer 242 is formed over the first and secondregions 206, 208 of the wafer 204. The patterned mask layer 242 can be aphotoresist layer patterned using standard lithographic techniques, andincludes at least one opening 244 over a channel 218 in the secondregion 208. The thick, first gate oxide 240 is etched in the exposedregions by using a BOE etch, under conditions similar to those describedabove with respect to removing the sacrificial oxide layer 234, and thepatterned mask layer 242 is then removed.

Referring to FIG. 2K, the wafer 204 is cleaned using a wet etch thatdoes not etch oxide in order to protect the first gate oxide 240 of theHV MOS transistor 212, and the blocking oxide layer 238 of the gatestack 236. The wafer 204 is then subjected to a thermal oxidationprocess to grow a thin, second gate oxide 246 having an appropriatethickness, such as from about 1 nm to about 3 nm. In some embodiments,the second gate oxide 246 can be overlaid with a deposited layer (notshown) such as silicon oxy-nitride, silicon nitride, aluminum oxide,hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate,hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide.

Referring to FIG. 2L, a gate layer 248 of any conducting orsemiconducting material suitable for accommodating a biasing of the NVMtransistor 226 and operation of the MOS transistors 214, 212, is formedover the gate stack 236, the first gate oxide 240 of the HV MOStransistor 214, and the second gate oxide 246 of the MOS transistor 212.In one embodiment, the gate layer 248 is formed by physical vapordeposition and is composed of a metal-containing material which mayinclude, but is not limited to, metal nitrides, metal carbides, metalsilicides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium,palladium, platinum, cobalt and nickel. In another embodiment, the gatelayer is formed by a CVD process and is composed of a single dopedpolysilicon layer, which may then be patterned to form control gates ofthe NVM transistor 226 and MOS transistors 214, 212.

Referring to FIG. 2M, the gate layer 248 is patterned using a mask layer(not shown) and standard lithographic techniques to stop on surfaces ofthe blocking oxide layer 238, the first gate oxide 240 and the secondgate oxide 246, thereby forming a gate 250 for the gate stack 236 of aNVM transistor 226, a gate 252 for the HV MOS transistor 214, and a gate254 for the MOS transistor 212.

Referring to FIG. 1 and FIG. 2N, a first spacer layer is deposited andetched to form first sidewall spacers 256 adjacent to the gates 252,254, of the MOS transistors 212, 214, and the NVM transistor 226, andone or more lightly-doped drain extensions (LDD 258) are implantedadjacent to and extend under sidewall spacers 256 of one or more of theMOS transistors 212, 214 (step 112).

Next, a SONOS LDD mask is formed over the wafer 204 and lightly-dopeddrain extensions (LDD 260) are implanted, adjacent to the NVM transistor226. Finally, a second spacer layer is deposited and etched to formsecond sidewall spacers 262 adjacent to the gate stack 236, of the NVMtransistor 226 (step 114).

In one or more alternative embodiments, fabrication steps as illustratedand described in FIGS. 1 to 2N may be adapted or modified to manufacturea floating gate based NVM transistor, instead of or additional of theSONOS based NVM transistor 226 in an integrated baseline CMOS process.

Referring to FIGS. 1 and 2O, with the NVM transistor 226, HV MOStransistor 214 and LV MOS transistor 212 substantially complete, sourceand drain implants are performed to form source and drain regions 264for all transistors and a silicide process performed (step 116). Asdepicted, silicide regions 266 may be formed on the exposed gates 250,252 and 254 and exposed source and drain regions 264. The silicideprocess may be any commonly employed in the art, typically including apre-clean etch, cobalt or nickel metal deposition, anneal and wet strip.

Referring FIG. 1 and FIG. 2O, optionally the method of fabricatingmemory cells including an embedded or integrally formed SONOS based NVMtransistor and MOS transistor(s) further includes the step of forming astress inducing layer or structure 268, such as a stress inducingnitride layer, over the gate stack 236 of the NVM transistor 226 toincrease data retention and/or to improve programming time andefficiency (step 118). In particular, inducing stress into thecharge-trapping layer 230 of the NVM transistor 226 changes energylevels of charge traps formed therein, thereby increasing chargeretention of the charge-trapping layer. In addition, forming a stressinducing structure 268, in or on the surface 216 of the wafer 204proximal to, and preferably surrounding, a region of the wafer in whichthe channel 224 of NVM transistor 226 is formed will reduce the bandgap, and, depending on the type of strain, increases carrier mobility.For example, tensile strain, in which inter-atomic distances in thecrystal lattice of the wafer 204 are stretched, increases the mobilityof electrons, making N-type transistors faster. Compressive strain, inwhich those distances are shortened, produces a similar effect in P-typetransistors by increasing the mobility of holes. Both of these straininduced factors, i.e., reduced band gap and increased carrier mobility,will result in faster and more efficient programming of NVM transistor226.

The strain inducing structure 268 can include a pre-metal dielectric(PMD) layer formed using a High Aspect Ratio Process (HARP™) oxidationprocess, a compressive or tensile nitride layer formed using a plasmaenhanced chemical vapor deposition (PECVD) or a Bis-Tertiary Butyl AminoSilane (BTBAS) nitride layer.

In certain embodiments, such as that shown in FIG. 2O, the stressinducing structure 268 may also be formed over one or more of the MOStransistors to induce strain in the channel of the MOS transistor.

Finally, the standard or baseline CMOS process flow is continued tosubstantially complete the front end device fabrication (step 120),yielding the structure shown in FIG. 2O. FIG. 2O is a block diagramillustrating a cross-sectional view of a portion of a finished memorycell including an embedded SONOS based NVM transistor and MOStransistors fabricated according to the method of FIGS. 1 and 2A-2N.

Thus, embodiments of memory cells including embedded or integrallyformed SONOS based NVM transistor and MOS transistors and methods offabricating the same have been described. Although the presentdisclosure has been described with reference to specific exemplaryembodiments, it will be evident that various modifications and changesmay be made to these embodiments without departing from the broaderspirit and scope of the disclosure. Accordingly, the specification anddrawings are to be regarded in an illustrative rather than a restrictivesense.

The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quicklyascertain the nature of one or more embodiments of the technicaldisclosure. It is submitted with the understanding that it will not beused to interpret or limit the scope or meaning of the claims. Inaddition, in the foregoing Detailed Description, it can be seen thatvarious features are grouped together in a single embodiment for thepurpose of streamlining the disclosure. This method of disclosure is notto be interpreted as reflecting an intention that the claimedembodiments require more features than are expressly recited in eachclaim. Rather, as the following claims reflect, inventive subject matterlies in less than all features of a single disclosed embodiment. Thus,the following claims are hereby incorporated into the DetailedDescription, with each claim standing on its own as a separateembodiment.

Reference in the description to one embodiment or an embodiment meansthat a particular feature, structure, or characteristic described inconnection with the embodiment is included in at least one embodiment ofthe circuit or method. The appearances of the phrase one embodiment invarious places in the specification do not necessarily all refer to thesame embodiment.

In the foregoing specification, the invention has been described withreference to specific exemplary embodiments thereof. It will, however,be evident that various modifications and changes may be made theretowithout departing from the broader spirit and scope of the invention asset forth in the appended claims. The specification and drawings are,accordingly, to be regarded in an illustrative sense rather than arestrictive sense.

What is claimed is:
 1. A method comprising: forming a dielectric stackon a wafer, wherein the dielectric stack includes a tunneling dielectricon the wafer, a charge-trapping layer, and a cap layer overlaying thecharge-trapping layer; patterning the dielectric stack to form anon-volatile gate stack of a non-volatile memory transistor in a firstregion of the wafer; removing the dielectric stack in a second region ofthe wafer; and performing a two-step gate oxidation process to oxidizeat least a first portion of the cap layer of the non-volatile gate stackto form a blocking oxide and form a gate oxide of at least onemetal-oxide-semiconductor transistor in the second region, wherein thegate oxide of the at least one metal-oxide-semiconductor transistor isformed during both a first oxidation step and a second oxidation step ofthe two-step gate oxidation process.